(Sr./Staff) ASIC Design Engineer

About this role

Key Responsibilities Key Responsibilities RTL Design and Verification Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection. Design and verify digital logic blocks such as test controllers, sequen

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• Design
• Engineering
• Computer Engineering
• Diagnostics
• Foundation Design
• RTL Coding

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