(Sr.) ISP RTL Design Manager

About this role

Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation Verify Logic at ISP level and Digital Sy

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• Engineering
• Signal and Image Processing
• Interpersonal Skills
• Digital Design
• RTL Design

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