Sr/ IC Design Engineer (Design Verification)

About this role

Job Descriptions Develop and Review Test Plan based on IC design specification Develop constrained-Random verification environment for complex DUT Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance Implement coverage matr

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• Engineering
• Sciences / Laboratory / R&D
• Design Verification
• Constrained-Random Verification
• Analytical Skills
• Design Test Plans

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