Senior/ IC Design Engineer (Design Verification)

About this role

Job Description Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications. Build and maintain SystemVerilog/ UVM-based verification environments and testbenches Develop directed and constrained-random tests, assertions(SVA), and functional coverage. De

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• Engineering
• Sciences / Laboratory / R&D
• Perl
• Analytical Approach
• Constrained-Random Verification
• Mixed-Signal IC Design