Senior / Staff Engineer - Digital Design

About this role

Your role Key responsibilities in your new role Perform RTL-to-gate synthesis using EDA tools such as Synopsys Design Compiler/Fusion Compiler or Cadence Genus to generate optimized gate-level netlists . Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages

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• Engineering
• Feasibility Studies
• Static Timing Analysis
• Medical Degree
• Collaborating With Designers

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