Packaging Engineer- Bump Interconnect
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Packaging Engineer- Bump Interconnect · SF Bay Area, United States
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About this role
We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure ana
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- Advanced Packaging
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