Physical Verification Sign-off Engineer

About this role

Job Description Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT,ERC, ESD, PERC) for tape-out Co-work with Place & Route team to resolve full-chip layout integration issues Coordinates with internal IP owners on IP related issues Coordinates with Manufacturing T

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• Engineering
• Perl
• Front-End Architecture
• Ip Addresses
• Tape Management

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